The feature size of integrated circuits has been aggressively reduced in the pursuit of improved speed, power, silicon area and cost characteristics (Rabaey, 1996). Semiconductor technologies with feature sizes of several tens of nanometers are currently in development. As per, International Technology Roadmap for Semiconductors (Semiconductor Industry Association. Online available at: http://public.itrs.net), the future nanometer scale circuits will contain more than a billion transistors and operate at clock speeds well over 10 GHz. Distributing robust and reliable power and ground; clock; data and address; and other control signals through interconnects in such a high-speed, high-complexity environment, is a challenging task.

Wide wires are frequently encountered in global and semi-global interconnects in upper metal layers. These wires are low resistive lines that can exhibit significant inductive effects (Ismail et al., 2001). Owing to presence of these inductive effects, the new generation VLSI designers have been forced to model interconnects as distributed RLC transmission lines (Deutsch et al., 1997; Ismail et al., 1999; Kahng and Muddu, 1997; Davis and Meindl, 2000). These RLC transmission line when running parallel to each other have capacitive and inductive coupling, which makes the design of interconnects even more important in terms of crosstalk. In a modern interconnect design, interconnects in adjacent metal layers are kept orthogonal to each other. This is done to reduce crosstalk as far as possible. But with growing interconnect density and reduced chip size, even the non-adjacent interconnects exhibit significant coupling effects. These coupling effects are significantly dependent on length of interconnects, distance between them, transition time of the input and the pattern of input.

On-chip inductance induced noise to signal ratio is increasing because of the increased switching speed, reduced separation between interconnects and reduced noise margins of devices. The impact of this noise, such as oscillation, overshoots and undershoots, has made chip's performance of concern in design. The effect of crosstalk induced overshoot and undershoot generated at a noise-site can propagate false switching and create a logic error (Banerjee and Mehrotra, 2001; Sinha et al., 2002). The false switching occurs when the magnitude of overshoot or undershoot is beyond the threshold of the gate. The peak overshoot and undershoot generated at a noise-site can wear out the thin gate oxide layer resulting in permanent failure of the chip. This problem will be significant as the feature size of transistor reduces with advancement of technology.

Reducing crosstalk is one of the important design perspectives for a VLSI interconnect designer. This paper for the first time shows the effect of voltage scaling on peak overshoot and undershoot in an inductively and capacitively coupled interconnect. Researchers have previously used voltage scaling for reduction of power dissipation at the cost of propagation delay (Kang and Leblebici, 2003). It is quite encouraging to observe that irrespective of technology node and length of interconnect; an optimized voltage scaling reduces normalized crosstalk level. This paper shows simulation results for crosstalk reduction in different nano-sized CMOS driven RLC-modeled interconnects.

For our studies we use a 130 nm technology with copper interconnects process. It is assumed that there are several metal layers available for the interconnects. It is well accepted that simulations of a distributed RLC model of an interconnect matches more accurately the actual behavior in comparison to a lumped RLC model. A distributed RLC model of an interconnect, known as the transmission line model, becomes the most accurate approximation of the actual behavior (Rabaey, 1996). The transmission line is, therefore, modeled by 20 distributed lumps. The capacitance and inductance values are obtained from (Delorme et al., 1996; Rosa, 1908; Lu et al., 2001). In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines (Figure 3) viz:

• Case A: V_A (input at aggressor node A) and V_B (input at victim node B) switching in same direction.
• Case B: V_A is switching and V_B at static low.
• Case C: V_A and V_B are switching in opposite direction.
• Case D: V_A is switching and V_B at static high.

The aggressor and victim lines driver and receiver sizes are shown in Figure 3. The W/L ratio above and below the gate in Figure 3 refers to PMOS and NMOS transistor, respectively. The channel length is 0.13 μm for all transistors. The predictive technology (online available at: www.eas.asu.edu/ ∼ ptm/) model files of PMOS and NMOS transistor for 130 nm technology is used. The experimental set up measures for maximum and minimum level of magnitude at output of transmission line, i.e. at load capacitance of receiver Vout2.

The rise and fall times for the input ramp is 50 ps. The terminating load capacitance of the aggressor (line-A) and victim (line-B) is 30 fF. Normalized peak over and undershoot values for both lines under four different cases of inputs are observed for various voltages (V_dd) from 1 to 5 V with a step of 0.5 V.

In this section, results for different simulating conditions are presented. The results are shown for each case with an interconnect length of 2 and 4 mm. Figures 4 and 5 show normalized max (V_max/V_dd) and normalized min (V_min/V_dd) under case-A type of stimulation for an interconnect length of 2 and 4 mm, respectively. It is observed that with increase in supply voltage normalized peak overshoot (V_max/V_dd) on line A and B decreases initially up to an optimum level and thereafter increases rapidly with increase in supply voltage, whereas, normalized peak undershoot (V_min/V_dd) goes on decreasing with increase in supply voltage. Thus, an optimum supply voltage exists where normalized peak over and under shoot level can be minimized.

Figures 6 and 7 show normalized max (V_max/V_dd) and normalized min (V_min/V_dd) under case-B type of stimulation for an interconnect length of 2 and 4 mm, respectively. Owing to static low input to driver of line B the line is forced at static high. Thus, overshoot voltages is of more concern on victim line as compared to undershoot voltages. Normalized peak overshoot for line B (which is at static high) reduces with voltage scaling. It is quite encouraging to observe that as supply voltage is reduced normalized peak overshoot also reduces. Since, line B is forced by driver output at static high, there is no undershoot below ground level, therefore, peak undershoot is not an important design concern for case B stimulations. Decrease in normalized peak overshoot (with 1 V supply) with respect to normalized peak overshoot (with 5 V supply voltage) is 56.33 percent and 61.82 percent for an interconnect length of 2 and 4 mm, respectively.

Figures 8 and 9 show normalized max (V_max/V_dd) and normalized min (V_min/V_dd) under case-C type of stimulation for an interconnect length of 2 and 4 mm, respectively. Both lines are switching in opposite direction. With increase in supply voltage normalized peak overshoot on line A and B decreases initially up to an optimum level and thereafter increases rapidly with increase in supply voltage. Normalized peak undershoot reduces rapidly as supply voltage is increased from 1 to 1.5 V for 2 mm length (from 1 to 2 V for 4 mm length). After this, the normalized peak undershoot remains approx. unchanged with supply voltage and is quite less also. Thus, in this case voltage scaling benefits can be derived only if an optimized voltage is selected.

Figures 10 and 11 show normalized max (V_max/V_dd) and normalized min (V_min/V_dd) under case-D type of stimulation for an interconnect length of 2 and 4 mm, respectively. Owing to static high input to driver of line B the line is forced at static low. Thus, undershoot voltages is of more concern as compared to overshoot voltages. Normalized peak undershoot on line B reduces as supply voltage is scaled. Normalized peak overshoot on line B is not of major concern since the overshoot does not go beyond the supply voltage. Hence, scaling supply voltage is always beneficial. Decrease in normalized undershoot (with 1 V supply) with respect to normalized undershoot (with 5 V supply voltage) is 49.77 percent and 47.2 percent for an interconnect length of 2 and 4 mm, respectively.

This paper for first time shows the effect of voltage scaling on crosstalk for various conditions of stimulations. It is quite encouraging to observe that irrespective of technology node used, an optimized voltage scaling reduces normalized crosstalk level. This paper shows simulation results for crosstalk reduction in different nano-sized CMOS driven RLC-modeled interconnects.

It is observed that as supply voltage is scaled for Case-B and D type of stimulations the overshoot and undershoot decreases, respectively. Thus, it is favorable to reduce supply voltage to lower the crosstalk level. For Case-A and C stimulations, an optimum supply voltage exists wherein the overshoot is minimum. Some adverse effect of voltage scaling is observed in Case-A where the undershoot level marginally increases as the supply voltage is scaled. Similarly for Case-C, the voltage scaling does have adverse effect on undershoots from supply voltage 1 to 1.5 V for 2 mm length and from 1 to 2 V for 4 mm length, for rest of the voltages the undershoot level is approximately constant. To conclude voltage scaling as a whole reduces crosstalk level.