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3D system-in-package design using stacked silicon submount technology

Mingzhi Dong (Beijing Research Center, Delft University of Technology, Beijing, China AND State Key Laboratory of Solid State Lighting, Beijing, China)
Fabio Santagata (Dongguan Institute of Opto-Electronics, Peking University, Dongguan, China AND Guangdong Dongguan Quality Supervision Testing Center, Dongguan, China)
Robert Sokolovskij (Beijing Research Center, Delft University of Technology, Beijing, China AND State Key Laboratory of Solid State Lighting, Beijing, China)
Jia Wei (Beijing Research Center, Delft University of Technology, Beijing, China AND State Key Laboratory of Solid State Lighting, Beijing, China)
Cadmus Yuan (Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China AND State Key Laboratory of Solid State Lighting, Beijing, China)
Guoqi Zhang (Delft Institute of Microsystems and Nanoelectronics (Dimes), Delft University of Technology, Delft, The Netherlands)

Microelectronics International

ISSN: 1356-5362

Article publication date: 5 May 2015

982

Abstract

Purpose

This study aims to provide a flexible and cost-effective solution of 3D heterogeneous integration for applications such as micro-electro-mechanical system (MEMS) applications and smart sensor systems.

Design/methodology/approach

A novel 3D system-in-package (SiP) based on stacked silicon submount technology was successfully developed and well-demonstrated by the fabrication and assembly process of a selected smart lighting module.

Findings

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The bonding and interconnecting process is quite simple and does not require complicated equipment. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. The submount wafer can be assembled and tested at the wafer level, thus reducing the cost and improving the yield.

Research limitations/implications

The embedding design presented in this paper is applicable for modules with limited number of passives. When it comes to cases with more passive devices, new process needs to be developed to achieve fast, inexpensive and reliable assembly.

Originality/value

The presented 3D SiP design is novel for applications such as smart lighting, Internet of Things, MEMS systems, etc.

Keywords

Acknowledgements

This work was supported by Guangdong Provincial Department of Science and Technology, China. The authors would like to thank Shanghai Institute of Microsystem and Information Technology (SIMIT), Chinese Academy of Sciences (CAS), for their assistance of silicon submount fabrication. The authors also would like to acknowledge the Institute of Microelectronics of Tsinghua University, China, for their support in the packaging process development.

Citation

Dong, M., Santagata, F., Sokolovskij, R., Wei, J., Yuan, C. and Zhang, G. (2015), "3D system-in-package design using stacked silicon submount technology", Microelectronics International, Vol. 32 No. 2, pp. 63-72. https://doi.org/10.1108/MI-11-2014-0050

Publisher

:

Emerald Group Publishing Limited

Copyright © 2015, Emerald Group Publishing Limited

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