ssmt10.1108/ssmtSoldering & Surface Mount Technology0954-0911Emerald Group Publishing Limited10.1108/ssmt.2012.21924baa.022e-non-articleSecondary articleNew productscat-ENGGEngineeringcat-EEEElectrical & electronic engineeringMultitest’s Ultraflat™ process meets requirements of high parallel vertical probe card applications06042012242© Emerald Group Publishing Limited2012peer-reviewednoacademic-contentyesrightslinkexcludedMultitest’s Ultraflat™ process meets requirements of high parallel vertical probe card applications

Article Type: New products From: Soldering& Surface Mount Technology, Volume 24, Issue 2

Multitest, a designer and manufacturer of final test handlers, contactors andload boards used by integrated device manufacturers (IDMs) and final testsubcontractors worldwide, announces that its UltraFlat™ process meets therequirements of high parallel vertical probe card applications.

For applications such as DDR3 memory, the requirements for the flatness ofboards at wafer-level testing become crucial. For optimizing MLO/MLC attachmentsand contact element interfaces, a better surface is needed. Additionally,flatter PCBs require less compliance from the probe interface and reduceinterface wear.

Leveraging the knowledge of PCB stack up engineering and PCB construction,Multitest developed the new “UltraFlat™” process to meet theserequirements. UltraFlat™ allows for a very tight overall flatnesstolerance to be maintained by removing the bow/twist in the PCB. Unlike “flat-baking”that provides a temporarily flat PCB, Mutltitest’s UltraFlat™ processprovides a permanent overall flatness for the PCB.

With UltraFlat™, Multitest typically is able to comply with bow/twistrequirements of 1.0 percent.

For more information, please visit: www.multitest.com/pcb