Circuit World

Cracking phenomena on flexible-rigid interfaces in PCBs under thermo cycling loading : Table of Contents

Luciano Arruda, Renato Bonadiman, Josineto Costa, Tommi Reinikainen — Sun May 17 14:15:04 BST 2009

Abstract:
Purpose – The purpose of this paper is to develop simulation models for flexible-printed circuit boards' flex-rigid interfaces and to perform experimental tests in the laboratory in order to evaluate the cracking phenomena when these devices are submitted to thermal cycling. Design/methodology/approach – A device was proposed in order to evaluate the reliability of flex-rigid interconnections. Thermal cycling tests were performed in an environmental chamber and failure mechanisms investigated using optical and scanning electron microscope techniques. The failure modes were analyzed using computational modelling via the finite element method. Findings – Through failure analysis, it was observed that device design and thermal expansion/contraction could contribute to the occurrence of high stresses in the copper pad connections. The simulation model proposed was able to identify the critical regions, as they had occurred in the tests. Thus, the qualitative approach may be considered successful enough to be applied in the early stages of design. Research limitations/implications – The materials proprieties were considered as being linear. Thus, in order to enhance the simulation models to provide a quantitative model for the evaluation of product life, non-linear (visco-elastic) behaviour in the material properties and a fracture model should be considered. Originality/value – Typical causes of cracking failure in electronic devices are related to mechanical stress, moisture, heat from transportation and field use. Thus, finite element analysis is an important tool in order to evaluate the reliability of electronic components regarding these types of loads in the early stages of design.

Reflow ageing influences and wettability effects of immersion tin final finishes with lead-free solder : Table of Contents

Thomas Hetschel, Klaus-Jürgen Wolter, Fritz Phillipp — Sun May 17 14:15:04 BST 2009

Abstract:
Purpose – The purpose of this paper is to investigate the oxidation behaviour of an immersion tin final finish after multiple reflow ageing under air and nitrogen atmospheres and to study their influence on the wetting behaviour with lead-free solder. To design a model that describes the degradation of wetting behaviour after reflow-cycling of the immersion tin final finish. Design/methodology/approach – A special printed circuit boards (PCB) demonstrator was created to investigate the immersion tin final finish with surface analysis methods and wetting tests. The PCB samples were aged by multiple reflow-cycling under air and nitrogen atmospheres. The tin oxide formation behaviour of immersion tin was characterised using X-ray photoelectron spectroscopy (XPS), transmission electron microscope (TEM) and SERA analysis. Findings – The native oxide layer of the investigated immersion tin final finishes was approximately 7?nm on average. The TEM and XPS investigations indicated an amorphous structure of SnO and SnO2. The solder spread test showed significantly different results for PCBs in “as received” condition compared to those after one and two times reflow ageing under a nitrogen solder atmosphere. The analysis methods revealed a slight increase in the tin oxide layer thickness and small areas with semi-crystalline structure. Reflow ageing under an ambient solder atmosphere induced considerably thicker oxide layers, which could be observed by a yellow discoloration of the surface. Research limitations/implications – Measures to improve the wetting behaviour can be derived from the described model (i.e. use of higher tin layer thickness or protective films to reduce the tin oxidation). Originality/value – A functional model for the solderability process of lead-free solder on immersion tin PCB final finishes was derived and verified. By this, interactions between the state of the final finish and the solder can be described and potential solderability failures can be predicted.

A multilayer process for the connection of fine-pitch-devices on molded interconnect devices (MIDs) : Table of Contents

Thomas Leneke, Soeren Hirsch, Bertram Schmidt — Sun May 17 14:15:04 BST 2009

Abstract:
Purpose – The purpose of this paper is to present a new multilayer process for three-dimensional molded interconnect devices (3D-MIDs) that allows the assembly of modern area array packaged semiconductors. Design/methodology/approach – A new 3D-MID multilayer process based on local overmolding is developed. To investigate this new process, a 3D demonstrator is designed, simulated and fabricated. Various technologies such as injection molding, maskless laser assisted electroless metallization, overmolding and laser via drilling are used. Findings – Using the new 3D-MID multilayer process a 3D demonstrator with three metallization layers is fabricated. Injection molding simulation is utilized to ensure a feasible demonstrator design. It is shown that a surface laser treatment improves layer-to-layer adhesion during the process. Shear and pull tests prove the adhesion promotion. The 3D fine-pitch-metallization is done down to 60?µm track width. Via resistance is measured by four terminal sensing in agreement with previous results. Design rules for process compatible vias are introduced. The fabricated demonstrator is suitable for flip-chip-based area array packaged semiconductors. Research limitations/implications – A proof of concept is given by the fabricated demonstrator. Further, work should include reliability tests of the multilayer structures and improvement of individual process steps. Originality/value – The paper describes a new multilayer process for 3D-MIDs. It overcomes existing restrictions regarding the electrical routing on 3D-MID surfaces. The compatibility of area array packaged semiconductors with a high-inputs/outputs count and the 3D-MID technology is improved.

A direct-writing approach to the micro-patterning of copper onto polyimide : Table of Contents

Sun May 17 14:15:04 BST 2009

Abstract:
Purpose – The purpose of this paper is to present a novel manufacturing process that aims to pattern metal tracks onto polyimide at atmospheric pressure and ambient environment. The process can be scaled up for industrial applications. Design/methodology/approach – From a thorough literature survey, different approaches were carried out for processing polyimide. Following a design of experiments for the processing and various characterisation techniques, a micro-coil was manufactured as a test demonstrator. Findings – The characteristics of some main formaldehyde-based electroless copper baths were compared. The quality of the sidewalls was characterised and the performance of the process was assessed. Originality/value – This paper demonstrates a high-value manufacturing technique that is mass manufacturable, low cost and suitable for use on 3D surfaces. Criteria required for the development of a direct-writing process have been described. The issues surrounding electroless plating on polyimide have been explained.

Low-power noise multilayer PCB with discrete decoupling capacitors inside : Table of Contents

Ki-Jae Song, Jongmin Kim, Jongwoon Yoo, Wansoo Nah, Jaeil Lee, Hyunseop Sim — Sun May 17 14:15:04 BST 2009

Abstract:
Purpose – The purpose of this paper is to present the power noise characteristics of a multilayer printed circuit board (PCB) in which discrete capacitors have been embedded. Design/methodology/approach – Embedded technology has been implemented on a multilayer PCB to enhance the performance and functionality and to decrease the power noise. Decoupling capacitors were directly positioned on the inner power planes of a board, which resulted in low-loop inductance through the minimized length of the interconnection from the chips to the PCB's power delivery network. Findings – A low-noise PCB was successfully designed and fabricated using an embedding process for the discrete decoupling capacitors. It was demonstrated that such an approach offers lower interconnection inductance and quiet noise performance, including highly efficient propagation noise suppression at wideband frequencies. Research limitations/implications – Most conventional simulation techniques offer expectations for the signal characteristics on the time domain to minimize bit error rates in application systems. Further development work will focus on the integrated simulation models including the equivalent circuits for the transmission line and power noise effects to improve the accuracy of the signal performance. Originality/value – This paper presents a new approach for improving generating and propagating noise performance through the use of an embedded decoupling capacitor design methodology.