Circuit World

OrmeSTAR Ultra – the organic metal nanofinish : Table of Contents

B. Wessling, M. Rischka, J. Posdorfer — Sat Jan 30 08:00:17 GMT 2010

Abstract:
Purpose – The purpose of this paper is to introduce a new class of surface finishes as an alternative to current final surface finishes. Design/methodology/approach – This new finish utilises nanotechnology and is based on a new formulation of the “organic metal” (OM). Findings – The final surface finish is an approximately 50?nm thin permanent layer, consisting of a complex between the OM and silver (Ag). Panels finished with OrmeSTAR™ Ultra show excellent solderability in spite of a low-layer thickness and therefore offer significant advantages over existing surface finishes. Originality/value – This new finish has proven to be a competitive alternative to current final finishes with excellent properties for soldering applications. The new nanotechnology can also significantly improve the environmental and economical consequences of solderable surface finishing.

Is “black pad” still an issue for ENIG? : Table of Contents

George Milad — Sat Jan 30 08:00:17 GMT 2010

Abstract:
Purpose – The purpose of this paper is to present a better understanding of nickel corrosion, also known as “black pad” during gold deposition of EN1G. Design/methodology/approach – This paper presents an accumulation of personal experience and observations of the problem over a period of ten years. It incorporates the experience of the Global Trade Association connecting the electronic industries (IPC) plating committee as it set out to write the IPC electroless nickel-immersion gold (ENIG) specification-4552. Findings – Understanding how corrosion occurs will go a long way in helping printed circuit board (PCB) manufacturers stay clear of the issue and make high quality ENIG finished PCBs. Research limitations/implications – The majority of the data presented has been substantiated. Originality/value – The paper details how, by good understanding of the mechanism of formation of corrosion products, manufacturers can steer clear from the problem.

Effectiveness of embedded capacitors in reducing the number of surface mount capacitors for decoupling applications : Table of Contents

Mohammed A. Alam, Michael H. Azarian, Michael Osterman, Michael Pecht — Sat Jan 30 08:00:17 GMT 2010

Abstract:
Purpose – The purpose of this paper is to present an analytical approach to find the reduction in the required number of surface mount capacitors by the use of embedded capacitors in decoupling applications. Design/methodology/approach – The analytical model used to perform decoupling is cavity model from theory of microstrip antenna and N-port impedance matrix. The methodology involves addition of decoupling capacitors between the power and the ground plane such that the impedance between ports on the power-ground plane becomes lower than the target impedance at that frequency. A case study is presented in which a 0.3?m×0.3?m power-ground plane is decoupled by using various combinations of surface mount capacitors and embedded capacitors in the frequency range of 0.001-1?GHz and at a target impedance of 0.1, 0.01, and 0.001?O. The total number of surface mount capacitors are compared in each case. Findings – Use of embedded planar capacitors with a thin dielectric (about 8?mm) dampened board resonances at high frequency, as compared to a thick dielectric. Embedded capacitors are found to reduce the number of surface mount capacitors when the target impedance is low and the operating frequency is high. Research limitations/implications – The methodology discusses in this paper is applicable to a simplified power-ground plane (which has no cut-outs and is rectangular in shape) as compared to actual digital circuits. Originality/value – This methodology can be used as a quick preliminary tool to evaluate the decrease in the number of surface mount capacitors (by the use of embedded capacitors) as compared to complex and time consuming electromagnetic solvers.

Inner-layer copper reliability of electroless copper processes : Table of Contents

Crystal P.L. Li, Paul Ciccolo, Dennis K.W. Yee — Sat Jan 30 08:00:17 GMT 2010

Abstract:
Purpose – The purpose of this paper is to present an overview of the alternative testing approaches that may be used to assess interconnect quality and their application to laminate material and plated-through-hole (PTH) process control. Design/methodology/approach – The paper introduces the importance of inner-layer copper reliability and how to evaluate it. It reviews and discusses the effects of all factors involved, including laminate material, panel design, and chemical controls, on interconnect defects (ICDs). Findings – The best possible reliability can only be achieved by implementation of process controls ranging from incoming laminate material inspection to drilling parameters and finally chemical controls within the electroless copper process. Research limitations/implications – This paper focuses on through-hole multilayer reliability. Although blind via reliability shares some aspects with through-hole reliability, there are other factors that only apply to blind vias. This area will be the subject of a future publication. Originality/value – The paper provides an overall review, integrating information on the whole electroless copper process, starting from ICD testing methods, and including the effects of laminate material, desmear, and PTH control. It provides a reference for readers involved in trouble shooting or process improvement.

Energy conservation and related best practices in printed circuit board (PCB) manufacturing : Table of Contents

Martin Goosey, Rod Kellner — Sat Jan 30 08:00:17 GMT 2010

Abstract:
Purpose – The purpose of this paper is to present the details of key best practices that can help printed circuit board (PCB) manufacturing companies to optimize energy consumption, conserve materials, and reduce waste and costs. Design/methodology/approach – Various individual opportunities for making energy saving are discussed along with the accompanying manufacturing best practices. Findings – There are many opportunities to reduce energy consumption across the whole PCB manufacturing process. Additional savings may also be made by enhancements to the broader activities within PCB manufacturing plants. Research limitations/implications – The paper summarises key findings that have been reported in a much larger Best Practice Guide and due to space considerations the amount of information given is somewhat restricted. Originality/value – The paper details how the introduction of best practices in each stage of the PCB manufacturing process can lead to material and energy savings that have value in helping board makers to reduce costs. Readers are directed to a larger Best Practice Guide which is freely available from the SurfEnergy web site.

Pilot trials of immersion silver deposition using a choline chloride based ionic liquid : Table of Contents

Sat Jan 30 08:00:17 GMT 2010

Abstract:
Purpose – The purpose of this paper is to present the optimisation of protocols for the immersion coating of silver onto copper-track printed circuit board (PCB) assemblies, using a novel class of ionic liquid and to show the implementation of the scale up process. Design/methodology/approach – Various conditions (temperatures and silver concentrations) are studied individually under laboratory conditions and then optimised for a pilot scale demonstrator line that is used to process British Standard test coupons. Findings – The use of these novel liquids for the immersion coating of silver produces silver dip coatings that are bright and even and which give solderability that is as good as the commercial aqueous, nitric acid based, electroless process without any solder-mask interface etching. Research limitations/implications – The combined technology has been optimised for an immersion silver coating line. Further development work should be undertaken to tailor the technology for gold immersion coating of PCB assemblies. Originality/value – The paper details a process in which no solder-mask interface etching is observed; that does not require the use of strong inorganic acids or expensive catalysts to sustain deposition and which does not appear to be light sensitive in contrast to other processes.