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<title>Microelectronics International  </title>


<link>http://www.emeraldinsight.com/1356-5362.htm</link>
<description> Table of Contents from the most recently published issues of Microelectronics International</description>
<language>en-us</language>
<copyright>2009 Emerald Group Publishing Ltd.</copyright>
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<title>Microelectronics International </title>
<url>http://www.emeraldinsight.com/info/pics/journals/mi-cover-xix.gif</url>
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<title>Electrical properties and electrical equivalent models of thick-film and LTCC microcapacitors : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960240</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; A capacitor is a basic electronic passive component. Thick-film technology allows manufacturing of capacitors covering the range of small and medium capacitances and they have been investigated in depth already. Low temperature co-fired ceramics (LTCC) technology makes it possible to fabricate buried capacitors, which leads to increased packaging density, but such components&#146; properties are not well known. The purpose of this paper is to present the results of investigations on thick-film and LTCC capacitors made in various technological variants. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Thick-film and LTCC capacitors were made in various technological variants. Different capacitor inks, metallurgy of electrodes and component constructions were investigated. Basic electrical properties and stability were determined. An electrical equivalent circuit of such components was developed based on frequency and temperature characteristics. &lt;B&gt;Findings&lt;/B&gt; &#150; Simple electrical equivalent circuits of self-made thick-film and LTCC micro-capacitors were developed based on measurements in frequency and temperature domain. Good fitting accuracy was obtained. The bulk material section of model is predominant in the low-frequency range. Interface region and serial resistance influence are revealed at higher frequency, affecting mainly dissipation factor value. Also, temperature and thermal ageing have affected strongly on that part of the model. &lt;B&gt;Originality/value&lt;/B&gt; &#150; The paper usefully examines the electrical properties and electrical equivalent models of thick-film and LTCC micro-capacitors.</description>
<author>Edward Mis, Andrzej Dziedzic, Karol Nitsch</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Influence of solution acidity on composition, structure and electrical parameters of Ni-P alloys : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960204</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to characterize electrical parameters of amorphous Ni-P resistive layers used for fabrication of precise resistors. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Ni-P resistive layers were produced by the chemical process in water solution using Ni&lt;UP&gt;2?+?&lt;/UP&gt; and H&lt;DN&gt;2&lt;/DN&gt;PO&lt;DN&gt;2&lt;/DN&gt;&lt;UP&gt;-&lt;/UP&gt; ions. The paper presents the results of the studies concerning the influence of bath acidity and conditions of thermal stabilization on the structure and temperature coefficient of resistance of Ni-P alloy. &lt;B&gt;Findings&lt;/B&gt; &#150; The temperature coefficient of resistance of amorphous Ni-P layers was found to depend significantly on the parameters of chemical metallisation process. It was stated that the changes of through-casing resistivity versus the acidity of technological solution have roughly parabolic characteristics. &lt;B&gt;Originality/value&lt;/B&gt; &#150; In this paper, it was at first explained how the changes of the structure of Ni-P resistive layers depend on their temperature coefficient of capacitance.</description>
<author>Z. Pruszowski, P. Kowalik, M. Ciez, J. Kulawik</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Comparison between models for &lt;IT&gt;p-n&lt;/IT&gt; junctions parameters extraction : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960222</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to compare different junctions' parameters extraction models. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; &lt;IT&gt;I-V&lt;/IT&gt; curves of &lt;IT&gt;p&lt;/IT&gt;&lt;UP&gt;&lt;IT&gt;+&lt;/IT&gt;&lt;/UP&gt;-&lt;IT&gt;n&lt;/IT&gt; and &lt;IT&gt;p&lt;/IT&gt;&lt;DN&gt;well&lt;/DN&gt;-&lt;IT&gt;n&lt;/IT&gt; diodes were measured. Five models for parameters extraction on I-V characteristics of diodes in an educational poly-Si gate p&lt;DN&gt;well&lt;/DN&gt; complementary metal oxide semiconductor (CMOS) technology were applied. The junctions' areas were 30?×?30?&lt;IT&gt;µ&lt;/IT&gt;m for the source-body &lt;IT&gt;p&lt;/IT&gt;&lt;UP&gt;+&lt;/UP&gt;-&lt;IT&gt;n&lt;/IT&gt; junction of the PMOS transistor and 220?×?250?&lt;IT&gt;µ&lt;/IT&gt;m for the p&lt;DN&gt;well&lt;/DN&gt;-body junction. The diodes were sintered in forming gas (10 percent of H&lt;DN&gt;2&lt;/DN&gt;) in the temperature interval of 450-525°C for times from 30?min up to 4?h. &lt;B&gt;Findings&lt;/B&gt; &#150; It was shown that the best annealing regimes are different for both kinds of junctions. &lt;B&gt;Originality/value&lt;/B&gt; &#150; The paper shows that the best annealing regime for &lt;IT&gt;p&lt;/IT&gt;&lt;UP&gt;+&lt;/UP&gt;-&lt;IT&gt;n&lt;/IT&gt; diodes (the lowest &lt;IT&gt;n&lt;/IT&gt; and &lt;IT&gt;I&lt;/IT&gt;&lt;DN&gt;&lt;IT&gt;0&lt;/IT&gt;&lt;/DN&gt; values) is 450°C, 30?min and for the &lt;IT&gt;p&lt;/IT&gt;&lt;DN&gt;well&lt;/DN&gt;-&lt;IT&gt;n&lt;/IT&gt; diodes (the lowest &lt;IT&gt;I&lt;/IT&gt;&lt;DN&gt;0&lt;/DN&gt; values) is 525°C, 60?min. So, for the different kinds of junctions in one integrated circuit, different annealings could give the best parameters and the optimization depends on the specific characteristics of the developed technology.</description>
<author>G.C. Pesenti, H. Boudinov</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Comparison of low cost, insulated aluminium substrates used as integrated heat sinks with conventional technology : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960178</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to describe two new thick film paste systems (one glass-based and the other polymer-based) for insulating aluminium substrates and allowing components like high-intensity light-emitting diodes to be attached to a conductor deposited on the dielectric. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Comparative measurements of the thermal resistance of different substrates mounted with metal-oxide semiconductor field-effect transistors were made. &lt;B&gt;Findings&lt;/B&gt; &#150; The thermal advantages of these two technologies have been proved. &lt;B&gt;Originality/value&lt;/B&gt; &#150; This paper presents useful comparative data from a replicated application using different combinations of substrates. The paper shows how the superior properties of the two new systems have been proven by thermal resistance measurements. From a thermal point of view, it is only the expensive 4?W?m&lt;UP&gt;-1&lt;/UP&gt;?K&lt;UP&gt;-1&lt;/UP&gt; insulated metal substrate that competes with the &#147;low cost&#148; systems.</description>
<author>E. Eisermann, K. Höll, W. Smetana, W. Tusler, M. Unger, J. Whitmarsh</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Polymer-metal nano-composite films for thermal management : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960213</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to present a novel nanostructured polymer-metal composite film providing continuous all-metal thermally conductive pathways, intended to meet future performance requirements on thermal interface materials (TIMs) in microelectronics packaging applications. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Porous polymer structures with a thickness of approximately 100?&lt;IT&gt;µ&lt;/IT&gt;m were manufactured using electrospinning technology. Pressure-assisted infiltration of low-melting temperature alloy into the porous polymeric carrier resulted in the final composite film. Thermal performance was evaluated using an accurate and improved implementation of the ASTM D5470 standard in combination with an Instron 5548 MicroTester. Finally, a brief comparative study using three current state-of-the-art commercial TIMs were carried out for reference purposes. &lt;B&gt;Findings&lt;/B&gt; &#150; Composite films with continuous all-metal thermally conductive pathways from surface to surface were successfully fabricated. Thermal resistances down to 8.5?K?mm&lt;UP&gt;2&lt;/UP&gt;?W&lt;UP&gt;-1&lt;/UP&gt; at 70?&lt;IT&gt;µ&lt;/IT&gt;m bond-line thickness were observed, corresponding to an effective thermal conductivity of 8?W?m&lt;UP&gt;-1&lt;/UP&gt;?K&lt;UP&gt;-1&lt;/UP&gt;, at moderate assembly pressures (200-800?kPa), more than twice the effective thermal conductivity of the commercial reference materials evaluated. &lt;B&gt;Originality/value&lt;/B&gt; &#150; A unique high-performance nanostructured polymer-metal composite film for TIM applications with the potential to meet the microelectronics industry's future demands on thermal performance and cost efficiency is presented.</description>
<author>Björn Carlberg, Teng Wang, Johan Liu, Dongkai Shangguan</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Silicon Schottky barrier photodiodes with a thin AlN nucleation layer : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960231</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to present the characteristics of novel silicon Schottky barrier (SB) photodiodes (PDs) with aluminium nitride (AlN) (100?nm) nucleation layer. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Comparison was made with conventional silicon SB PDs. &lt;B&gt;Findings&lt;/B&gt; &#150; It was found that smaller dark current could be achieved with AlN nucleation layer. It was also found that effective SB height increased from 0.65 to 0.71?eV with the insertion of the AlN layer. The dark leakage current for the Schottky PDs with the AlN layer was shown to be about two orders of magnitude smaller than that for the conventional silicon SB PDs. &lt;B&gt;Research limitations/implications&lt;/B&gt; &#150; It is possible that the detrimental effect of interface states situated near the metal semiconductor interface was less pronounced for the sample owing to the insertion of the AlN nucleation layer. &lt;B&gt;Originality/value&lt;/B&gt; &#150; There is believed to be no other report on silicon SB PDs capped with an AlN layer in the literature. This paper describes the fabricated silicon SB PDs and reports on the electrical characteristics of the devices with an AlN nucleation layer grown at low temperature.</description>
<author>L.S. Chuah, Z. Hassan, H. Abu Hassan, C.W. Chin, S.M. Thahab, S.C. Teoh</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Fine and ultra-fine pitch wire bonding: challenges and solutions : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960187</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to review recent advances in fine and ultra-fine pitch wire bonding. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Dozens of journal and conference articles published recently are reviewed. &lt;B&gt;Findings&lt;/B&gt; &#150; The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non-sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra-fine pitch wire bonding are discussed. &lt;B&gt;Research limitations/implications&lt;/B&gt; &#150; Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details. &lt;B&gt;Originality/value&lt;/B&gt; &#150; This paper attempts to provide an introduction to recent developments and the trends in fine and ultra-fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.</description>
<author>Z.W. Zhong</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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<title>Ruthenium dioxide doped manganite-based NTC thermistors for low-resistance applications : Table of Contents</title>
<link>http://www.emeraldinsight.com/10.1108/13565360910960196</link>
<description> &lt;B&gt;Abstract:&lt;/B&gt;&lt;BR/&gt; &lt;B&gt;Purpose&lt;/B&gt; &#150; The purpose of this paper is to study the properties of disc type negative temperature coefficient (NTC) thermistors based on the spinel system Mn-Co-Ni-O with the doping of RuO&lt;DN&gt;2&lt;/DN&gt; for the low-resistance applications. &lt;B&gt;Design/methodology/approach&lt;/B&gt; &#150; Emphasis was placed on the properties of ruthenium dioxide doped manganite spinel system for low-resistance applications. The properties such as microstructure, X-ray diffraction analysis and electrical properties are reported. &lt;B&gt;Findings&lt;/B&gt; &#150; The prepared NTC thermistor compositions revealed the room temperature resistance and thermistor constant in the range of 28-2,950?O and 1,539-3,428?K, respectively. Hence, the prepared NTC thermistors with low resistance and moderate sensitivity are suitable from an industrial applications point of view. &lt;B&gt;Originality/value&lt;/B&gt; &#150; The paper reports upon a synthesis procedure which is a straightforward preparation of highly densified ternary oxide (Mn-Co-No-O) thermistors.</description>
<author>Shweta Jagtap, Sunit Rane, Suresh Gosavi, Dinesh Amalnerkar</author>
<pubDate>Sun May 03 14:15:07 BST 2009</pubDate>
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