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Systematic layout planning: a study on semiconductor wafer fabrication facilities

Taho Yang (National Cheng Kung University, Tainan, Taiwan)
Chao‐Ton Su (National Chiao Tung University, Hsinchu, Taiwan)
Yuan‐Ru Hsu (National Chiao Tung University, Hsinchu, Taiwan)

International Journal of Operations & Production Management

ISSN: 0144-3577

Article publication date: 1 November 2000

6915

Abstract

This paper proposes to use Muther’s systematic layout planning procedure as the infrastructure to solve a fab layout design problem. A multiple objective decision making tool, analytic hierarchy process, is then proposed to evaluate the design alternatives. The proposed procedure is illustrated to be a viable approach for solving a fab layout design problem through a real‐world case study. It features both the simplicity of the design process and the objectivity of the multiple‐criteria evaluation process as opposed to existing solution methodologies.

Keywords

Citation

Yang, T., Su, C. and Hsu, Y. (2000), "Systematic layout planning: a study on semiconductor wafer fabrication facilities", International Journal of Operations & Production Management, Vol. 20 No. 11, pp. 1359-1371. https://doi.org/10.1108/01443570010348299

Publisher

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MCB UP Ltd

Copyright © 2000, MCB UP Limited

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