Solder void size reduction in semiconductor package by vacuum reflow and pressure cure processes
Soldering & Surface Mount Technology
ISSN: 0954-0911
Article publication date: 26 January 2022
Issue publication date: 17 June 2022
Abstract
Purpose
Semiconductor packaging industry has in recent years tightened the tolerance criteria for acceptable solder void size in the semiconductor packages due to the high usage in automotive applications. Semiconductor packaging component makers have strengthened the quality of the solder joint and its electrical conductivity by controlling the maximum solder void size reduction from 10-15% to 5% or below over die size. This paper aims to reduce the solder void size to minimum level that current industry could not achieve and introduce a new soldering processes by combining vacuum reflow and pressure cure to effectively reduce solder void.
Design/methodology/approach
This study is using the empirical data collection to prove the feasible in achieve the goal. It is an engineering approach. This research study is even considering sufficient data (>22 units) in each evaluation to represent the actual performance.
Findings
Successfully eliminate all the hollow solder void that current industry claimed as solder void. EDX analysis showed that the compressed solder voids remained in the solder are filled with solid carbon-based substances which could be originated from the trapped flux residues. It is empirical data proven in feasibility stage.
Research limitations/implications
The study is able to produce solder void-less. This method is suitable for high volume manufacturing process also. This may lead a new pave way for industry to resolve solder void problem. The current pressure cure machine could not apply more than 200°C temperature which limits medium and high temperature solder paste or alloy testing. Therefore, only low temperature solder alloy Pb37Sn63 was able to be evaluated.
Originality/value
This study is original and has not been published elsewhere to produce high efficiency product in semiconductor packaging performance in electrical path and heat dissipation. It also improves package reliability due to solder joint used as interconnect in semiconductor packaging.
Keywords
Acknowledgements
This research work would not have been possible without the exceptional support from Heller Industries, through the provision of reflow and pressure cure machines to build the test samples as well as information sharing for the machine and process operations. The authors would also like to thank Ms X.H. Ho for her technical support in the failure analysis activity, as well as Mr H.C. Cheam, a Six Sigma Master Black Belt for his expert advice in learning the technique of statistical analysis.
Citation
Yeo, S.M., Yow, H.K. and Yeoh, K.H. (2022), "Solder void size reduction in semiconductor package by vacuum reflow and pressure cure processes", Soldering & Surface Mount Technology, Vol. 34 No. 4, pp. 239-254. https://doi.org/10.1108/SSMT-05-2021-0018
Publisher
:Emerald Publishing Limited
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