Comparative performance analysis of AES encryption algorithm for various LVCMOS on different FPGAs
ISSN: 1708-5284
Article publication date: 15 February 2022
Issue publication date: 4 July 2023
Abstract
Purpose
Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing.
Design/methodology/approach
This paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz).
Findings
The comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design.
Originality/value
The green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.
Keywords
Acknowledgements
Authors would like to thank Dr Shilpi Bisht, Assistant Professor (Mathematics), Birla Institute of Applied Sciences, Bhimtal, India for her advice and guidance in mathematical modeling of the proposed design. They express their gratitude to the reviewers for the insightful comments that had helped in improving the quality of the paper.
Corrigendum: It has come to the attention of the publisher that the article Bisht, N., Pandey, B. and Budhani, S.K. (2023), “Comparative performance analysis of AES encryption algorithm for various LVCMOS on different FPGAs”, World Journal of Engineering, Vol. 20 No. 4, pp. 669-680. https://doi.org/10.1108/WJE-05-2021-0281, did not include all affiliations for Neeraj Bisht. This error was introduced during the submission process. Neeraj Bisht, Department of Computer Science, Birla Institute of Applied Sciences, Bhimtal, India has been changed to Neeraj Bisht, Department of Computer Science, Birla Institute of Applied Sciences, Bhimtal, India and Research Scholar, Graphic Era Hill University, Bhimtal Campus, India. The authors sincerely apologise for this error and for any misunderstanding.
Citation
Bisht, N., Pandey, B. and Budhani, S.K. (2023), "Comparative performance analysis of AES encryption algorithm for various LVCMOS on different FPGAs", World Journal of Engineering, Vol. 20 No. 4, pp. 669-680. https://doi.org/10.1108/WJE-05-2021-0281
Publisher
:Emerald Publishing Limited
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