Efficient bus based router for NOC architecture

Abstract

Purpose

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the network-on-chip (NOC) architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand, true fully adaptive routing algorithm provides routing of packets completely based on traffic conditions. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of a global bus beside NOC as a parallel supportive environment provides a platform to offer advantages of both features of bus and NOC.

Design/methodology/approach

In this research, the authors use this bus as an escaping path for deadlock recovery technique.

Findings

According to simulation results, this bus is a suitable platform for a deadlock recovery technique.

Originality/value

This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services.

Citation

Shrivastava, A. and Sharma, S.K. (2016), "Efficient bus based router for NOC architecture", World Journal of Engineering, Vol. 13 No. 4, pp. 370-375. https://doi.org/10.1108/WJE-08-2016-049