Good quality and high reliability are not an accident!

Citation

Starkey, P. (2010), "Good quality and high reliability are not an accident!", Circuit World, Vol. 36 No. 2. https://doi.org/10.1108/cw.2010.21736bac.002

Good quality and high reliability are not an accident!

Article Type: Exhibitions and conferences From: Circuit World, Volume 36, Issue 2

SMART Group Seminar on High-End PCBs, National Physical Laboratory, UK, 17 November 2009

“Good quality and high reliability are not an accident: they are there by design!” were the opening words of Artetch Circuits MD Martin Morrell as he introduced the SMART Group seminar on high-technology, high-reliability printed circuit boards (PCBs) at the UK’s National Physical Laboratory on 17 November 2009. “Understanding your product, the materials used in its production and how it is manufactured are crucial in designing cost effective products with high reliability” he continued, addressing an attentive audience of PCB designers. He highlighted SMART Group’s role in facilitating the sharing of knowledge and understanding of products, materials and processes in the electronics industry, and the support of NPL in partnering industry through research and studio projects. He referred in particular to the establishment of the NPL Defect Data Base, http://defectsdatabase.npl.co.uk an open resource enabling the electronics industry to gather and categorise data on process defects and field failures, to monitor their frequency and to assist in their elimination.

The well-balanced seminar programme covered many aspects relevant to printed circuit design and included presentations on materials for high-end PCBs, specifying PCBs in fabricators’ language, finishes for wire-bonding and soldering, specifications and approvals, PCBs for military and aerospace applications, the outcome of reliability testing projects, and methods of calculating, specifying and testing electrical impedance characteristics of PCBs.

First presentation came from Alun Morgan, Director of OEM Marketing with Isola, who described the influence of the three component materials: glass, resin and foil, on the thermal and electrical properties of laminates. He made some interesting observations on the effects of foil treatment on signal loss at high frequencies. At 10 GHz, the signal is carried not in the bulk cross-section of a copper trace, but in a layer less than 1 μm deep in the “skin” of the conductor. The comparative roughness of the bonding treatment on conventional foil led to substantial loss, and drum-side-treated foil was now preferred in high-frequency applications. Dielectric losses had also been reduced by improvements in the manufacture of glass fabric to give a more uniform distribution of glass filaments, On the subject of thermal reliability, particularly in a lead-free soldering context, Morgan referred to thermo-mechanical and thermo-gravimetric analysis techniques for determining glass transition and decomposition temperatures, and pointed out that a high Tg did not, in itself, infer high thermal reliability. There had been a wholesale adoption of phenolic curing systems for epoxy laminates since the advent of lead-free soldering, and these gave enormous improvements in thermal stability over conventional dicyandiamide systems.

Dennis Price, Quality Director of Merlin Circuit Technologies, is a leading spokesman on overcoming the difficulties encountered in communicating printed circuit requirements from design to manufacture, and explained step by step the complex sequence of events from request-for-quotation and purchase order receipt to the output of manufacturing, test and inspection data. He listed minimum data requirements and preferred data formats, and discussed materials specifications, commenting that material availability had become a major issue and that the customer stood the best chance of achieving early delivery of his PCBs if he specified laminates generically by IPC-4101 slash-sheet numbers rather than by calling-up specific brand names. Delays resulting from missing or incorrect engineering information continued to be a regular problem, as did all the issues related to design-rule violations revealed by routine design-for-manufacture checks.

Terry Bateman, Project Manager with Optiprint described the benefits of chip-on-board with direct gold-wire-bonding for assemblies operating at frequencies up to 90 GHz, and reviewed cost-effective conductor finishes offering reliable wire-bondability in combination with solderability and mechanical durability. Electroless nickel/electroless palladium/immersion gold, with 3-5 μm nickel, 0.2-0.5 μm palladium and 0.03 μm gold, was a good general-purpose finish but could tend to be “lossy” at high frequencies, and nickel spread was sometimes a problem on ceramic-filled PTFE substrates. The plating chemistry needed a steady throughput of work to ensure consistent deposition. Electroless nickel/thick electroless gold, with 3-5 μm nickel and up to 0.9 μm gold was a lower loss finish, wire bondable and solderable without significant gold embrittlement, but was 30 per cent more expensive and still showed some nickel-spread effects. Further limitations of nickel-based finishes were brittleness and a tendency to reduce the peel strength of conductors. The recently introduced electroless silver/immersion gold finish, with silver up to 1 μm and a 0.03 μm gold flash, offered the lowest RF losses due to the absence of nickel and the high conductivity of silver, reliable gold-wire bonding and excellent solderability with a long shelf life.

Neil Stanton of BSI gave a perspective on approvals and standards for PCBs from the standpoint of a major certification body, beginning by advising some caution in accepting terms such as “accreditation”, “certification”, “approval”, “meets the requirements of” or “released to” without seeing up-to-date documentary authentication. He reviewed the various categories of approval: systems approvals, product approvals and process approvals, and summarised the many standards relating to PCBs: national, European and international, which generally cross-referenced other standards and specifications. Taking as examples the BS 12300, BS EN 123000 and IPC-6011 generic specifications and their related sectional specifications, he then discussed the mechanism of qualification, technology or capability approval under the internationally recognised IECQ component qualification scheme. His concluding advice was to know what you are specifying and why, to understand the limits of the standard, and always remember what you are trying to achieve.

Paul Comer, Technical Director of Graphic, explained some of the technology and reliability requirements of PCBs for military and aerospace requirements, with reference to military fixed-wing, military rotary-wing, marine, land-based, weapon, civil aviation and space applications. He reviewed quality and acceptability to standards including MIL-PRF-31032, MIL-PRF-55110, MIL-P-50884 and IPC 6011 Series Class 3, with a comment that certain design features do not allow these requirements to be achieved, minimum annular ring dimension being a particular example. In addition to maintaining their military approvals, graphic subscribed to a change programme named SC21, specific to the aerospace and defence industry, designed to accelerate the competitiveness of the industry by raising the performance of its supply chains, and overseen by Society of British Aerospace Companies Enterprise Excellence Board. Current technology in military PCBs included rigid, flex-rigid and mixed-material designs featuring various microvia configurations: copper filled, resin filled, capped, stacked and stacked-on-capped, as well as embedded resistance and functional dielectrics. Comer discussed the influence of aspects of design, materials, processing and finishing, and discussed methods and procedures for demonstrating and proving reliability.

Martin Wickham gave an update on four PCB reliability-testing projects undertaken at the National Physical Laboratory: via reliability, delamination, copper dissolution and conductive anodic filament formation (CAF). The results indicated that via reliability could be improved by reducing via aspect ratio, reducing peak reflow temperature, reducing PCB thickness, reducing the number of thermal excursions and using substrate material with increased glass transition temperature and reduced z-axis thermal expansion coefficient above glass transition. Ironically, all these factors might be secondary to the capability of the particular fabricator making the boards! Delamination of multilayer boards had been shown to result primarily from moisture ingress, which vapourised and ruptured the multilayer construction during soldering and rework operations. Work was in hand to develop test methods to enable non-destructive go/no-go pre-assembly checking of PCBs, and to provide industry with a best practice guide on how to minimise the effects of lead-free reflow profiles on substrate integrity. A joint industry project to study copper dissolution during soldering, either by erosion or by leaching, had shown dissolution rate to depend on temperature, flow rate, copper type and alloy composition. When different alloying elements were added to solder, there was an inverse correlation between dissolution rate and the thickness of intermetallic compound. Having completed one major study, NPL was embarking upon a new three-year collaborative project to develop a better understanding of conductive anodic filament effects, and to characterise PCB material, design and process issues.

“All models are wrong, but some are useful!” Neil Chamberlain, European Sales Manager with Polar Instruments gave a comprehensive introduction to the use of modelling and field-solving techniques in calculating impedance, and explained how to meaningfully specify and communicate impedance requirements from designer to PCB fabricator with clear documentation, whilst leaving the fabricator scope to compensate for non-homogeneous material effects and process tolerances. He discussed the design of realistic coupons to enable process conformance testing, and emphasised that testing is primarily for manufacturing verification rather than design verification. Time-domain reflectometry remained the industry-standard for impedance testing, but future test methods would take into account losses in high-speed traces.

The wealth of information delivered by the presenters formed the basis for an energetic and productive panel discussion, moderated by Dr Chris Hunt, as members of the audience posed challenging questions on materials specifications, the suitability of microvia technologies for high-reliability applications, the effects of material structure on real-life impedance calculation and the influence of design details on interconnection and solder joint reliability. An enlightening experience: everyone, not only delegates but presenters too, broadened their knowledge base, and a room-full of PCB designers left the seminar with a clearer appreciation of the realities to be taken into consideration when designing their products and specifying their requirements.

Pete StarkeyEAB member, Circuit World