MAPPING OF INTERNAL DISTRIBUTIONS ONTO A LUMPED ELEMENT NETWORK FOR CMOS LATCH‐UP SIMULATION

Abstract

An efficient device simulation method is presented, which has been derived from mapping the results of a complete two‐dimensional (2‐D) analysis onto an equivalent lumped element network. The method is currently being used to predict latch‐up sensitivities of CMOS process design.

Citation

WERNER, C., HARTER, J., TAKACS, D. and WIEDER, A.W. (1983), "MAPPING OF INTERNAL DISTRIBUTIONS ONTO A LUMPED ELEMENT NETWORK FOR CMOS LATCH‐UP SIMULATION", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 2 No. 4, pp. 195-206. https://doi.org/10.1108/eb009983