Search
  Advanced Search
 
Journal search
Journal cover: Microelectronics International

Microelectronics International

ISSN: 1356-5362

Online from: 1982

Subject Area: Electrical & Electronic Engineering

Content: Latest Issue | icon: RSS Latest Issue RSS | Previous Issues

Options: To add Favourites and Table of Contents Alerts please take a Emerald profile

Previous article.Icon: Print.Table of Contents.Next article.Icon: .

Repeater insertion in global interconnects in VLSI circuits


Document Information:
Title:Repeater insertion in global interconnects in VLSI circuits
Author(s):Rajeevan Chandel, (Electronic & Computer Engineering, Indian Institute of Technology, Roorkee, India), S. Sarkar, (Electronic & Computer Engineering, Indian Institute of Technology, Roorkee, India), R.P. Agarwal, (Electronic & Computer Engineering, Indian Institute of Technology, Roorkee, India)
Citation:Rajeevan Chandel, S. Sarkar, R.P. Agarwal, (2005) "Repeater insertion in global interconnects in VLSI circuits", Microelectronics International, Vol. 22 Iss: 1, pp.43 - 50
Keywords:Circuit properties, Electronically operated devices, Voltage
Article type:General review
DOI:10.1108/13565360510575549 (Permanent URL)
Publisher:Emerald Group Publishing Limited
Abstract:

Purpose – Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage-scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Design/methodology/approach – Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Findings – Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage-scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage-scaling. This leads to area and further power saving.

Research limitations – The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

Originality/value – The paper is of high significance in VLSI design and low-power high-speed applications. It is also valuable for new researchers in this emerging field.



Fulltext Options:

Login

Login

Existing customers: login
to access this document

Login


- Forgot password?
- Athens/Institutional login

Purchase

Purchase

Downloadable; Printable; Owned
HTML, PDF (191kb)Purchase

To purchase this item please login or register.

Login


- Forgot password?

Recommend to your librarian

Complete and print this form to request this document from your librarian


Marked list


Bookmark & share

Reprints & permissions