Online from: 1982
Subject Area: Electrical & Electronic Engineering
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|Title:||Low voltage four-quadrant analog multiplier using dynamic threshold MOS transistors|
|Author(s):||Vandana Niranjan, (Electronics and Communication Engineering, Indira Gandhi Institute of Technology, GGSIP University, New Delhi, India), Maneesha Gupta, (Electronics and Communication Engineering, Netaji Subhash Institute of Technology, Delhi University, New Delhi, India)|
|Citation:||Vandana Niranjan, Maneesha Gupta, (2009) "Low voltage four-quadrant analog multiplier using dynamic threshold MOS transistors", Microelectronics International, Vol. 26 Iss: 1, pp.47 - 52|
|Keywords:||Integrated circuits, Signal processing, Voltage|
|Article type:||Research paper|
|DOI:||10.1108/13565360910923179 (Permanent URL)|
|Publisher:||Emerald Group Publishing Limited|
Purpose – Real-time multiplication of two analog signals is one of the most important operations in analogue signal processing. Driven by low-power and low-voltage requirements for integrated mixedsignal portable applications, the paper's aim is to propose a novel four-quadrant low-voltage analog multiplier using dynamic threshold MOS transistors (DTMOS).
Design/methodology/approach – The SPICE simulations were performed with 0.25?µm technology parameters and results verify the performance of the circuit. The multiplier is simulated at low-supply voltage of ±0.5?V.
Findings – The proposed multiplier has high linearity and simple structure hence it is suitable for high-performance and low-power analog VLSI applications.
Originality/value – A new low-voltage four quadrant analog multiplier using DTMOS circuit topology is presented in the paper.
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