Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology

This paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.

A new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.

The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.

The proposed bit-cell is novel compared with existing bit-cells.