Modeling dc gain performance of 4H‐SiC BJTs

Abstract

Purpose

To model the differential dc gain, base resistance, and current voltage performance of 4H‐Silicon Carbide (SiC) bipolar junction transistors (BJT) operating at and above room temperature. Accurate modeling will result in improved process efficiency, interpretation of experimental data, and insight into device behavior.

Design/methodology/approach

The PISCES two dimensional device simulation program is used to allow for modeling the behavior of 4H‐SiC BJT. The physical material parameters in PISCES such as carrier's mobility and lifetime, temperature dependent bandgap, and the density of states are modified to accurately represent 4H‐SiC. The simulation results are compared with the measured experimental data obtained by others. The comparisons made with the experimental data are for two different devices that are of interest in power electronics and RF applications.

Findings

The simulation results predict a dc current gain of about 25 for power device and a gain of about 20 for RF device in agreement with the experimental data. The comparisons confirm the accuracy of the modeling employed.

Research limitations/implications

The simulated current‐voltage characteristics indicate that higher gain may be achieved for 4H‐SiC transistors if the leakage current is reduced.

Practical implications

The simulation work discussed in this paper complements the current research in the design and characterization of 4H‐SiC bipolar transistors. The model presented will aid in interpreting experimental data at a wide range of temperatures.

Originality/value

This paper reports on a new model that provides insight into the device behavior and shows the trend in the dc gain performance important for the design and optimization of 4H‐SiC bipolar transistors operating at or above the room temperature.

Citation

Fardi, H.Z. (2007), "Modeling dc gain performance of 4H‐SiC BJTs", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 26 No. 5, pp. 1236-1246. https://doi.org/10.1108/03321640710822984