Comparison between models for p‐n junctions parameters extraction

Abstract

Purpose

The purpose of this paper is to compare different junctions' parameters extraction models.

Design/methodology/approach

I‐V curves of p⁺‐n and p_well‐n diodes were measured. Five models for parameters extraction on I‐V characteristics of diodes in an educational poly‐Si gate p_well complementary metal oxide semiconductor (CMOS) technology were applied. The junctions' areas were 30 × 30 μm for the source‐body p⁺‐n junction of the PMOS transistor and 220 × 250 μm for the p_well‐body junction. The diodes were sintered in forming gas (10 percent of H₂) in the temperature interval of 450‐525°C for times from 30 min up to 4 h.

Findings

It was shown that the best annealing regimes are different for both kinds of junctions.

Originality/value

The paper shows that the best annealing regime for p⁺‐n diodes (the lowest n and I₀ values) is 450°C, 30 min and for the p_well‐n diodes (the lowest I₀ values) is 525°C, 60 min. So, for the different kinds of junctions in one integrated circuit, different annealings could give the best parameters and the optimization depends on the specific characteristics of the developed technology.

Citation

Pesenti, G.C. and Boudinov, H. (2009), "Comparison between models for p‐n junctions parameters extraction", Microelectronics International, Vol. 26 No. 2, pp. 37-40. https://doi.org/10.1108/13565360910960222