Fifth generation MIL-STD-1553 terminal

Citation

(2000), "Fifth generation MIL-STD-1553 terminal", Aircraft Engineering and Aerospace Technology, Vol. 72 No. 3. https://doi.org/10.1108/aeat.2000.12772cad.001

Fifth generation MIL-STD-1553 terminal

Keywords DDC, Data bus, Defence, Aircraft

DDC has introduced a fifth generation MIL-STD-1553 terminal which they believe represents the highest level of integration of this function to date (Plate 1). The circuit serves as an interface between a host processor and the MIL-STD-1553 data bus which is used on virtually all of the Western World's military aircraft and in a wide variety of other defence equipment.

Plate 1 DDC's fifth generation MIL-STD-1553 terminal

Backwards compatible with DDC's Mini-ACE and Mini-ACE Plus for legacy applications, the enhanced model claims additional functionality in many areas. Enhanced Mini-ACE configurations include RT only and BC/RT/MT versions with 4K words of internal RAM, 64K-word internal RAM with RAM parity checking.

Enhanced Mini-ACE units are packaged in one-square-inch ceramic flatpaks providing compatibility with the Mini-ACE. The enhanced units are available with a choice of 5V or 3.3V internal logic, and 5V transceivers with options for 1553, McAir, or MIL-STD-1760 compatibility.

The enhanced Mini-ACE's BC architecture includes an internal message sequence control processor, a general purpose queue, and user-definable interrupts.

The internal processor's 20-instruction set includes conditional operations based on results of messages or user-defined flags, along with jumps, subroutine calls, and timing control. This reportedly enables a highly autonomous capability for operations such as minor and major frame generation, asynchronous message transmission, flexibility in data buffering, and message retry and bus-switching strategies.

The flag bits, general purpose queue, and user-definable interrupts program a high degree of flexibility in reporting message status, timing, and data information from the BC to the host processor.

The RT architecture provides multiprotocol flexibility for MIL-STD-1553 (Notice 2), STANAG 3838, and McAir, as well as a wide choice of memory management options. These include subaddress single buffering, double buffering for individual receive subaddresses, circular buffering for individual subaddresses, and an option for global circular buffering for multiple (or all) subaddresses. The selective MT monitor mode provides message filtering based on RT address, T/R bit, and subaddress.

The RT and selective monitor, which can work concurrently, can provide interrupts at 50 per cent and 100 per cent rollover which enable the RT/monitor and the host to alternately access different multi-message areas of shared RAM.

Like the ACE and Mini-ACE, the enhanced Mini-ACE supports a variety of host interface configurations. These include shared RAM and DMA configurations; direct connections to 8-, 16-, and 32-bit processors; support of multiplexed or non-multiplexed address/data buses; and interfaces to either microprocessor memory buses or microcontroller I/O ports, without external buffers and with a minimum of "glue" logic.

In comparison with the ACE/Mini-ACE, the enhanced Mini-ACE reduces the host's maximum hold-offtime for a shared RAM host interface, and increases the maximum request-to-grant time for a DMA interface. The interrupt request output may be configured to provide a choice of a pulse- or level-type signal.

The enhanced Mini-ACE can operate from a choice of 10, 12, 16, or 20MHz clock inputs. A comprehensive built-in self-test includes fully autonomous verification of the encoder/decoder, registers, transmitter watchdog timer, and protocol.

There is a separate built-in self-test for exercising the 4K or 64K internal RAM. Other features include a large set of interrupt conditions, an interrupt status queue for RT and MT modes with filtering based on valid and/or invalid messages, multiple options for time tagging, and an RT auto-boot feature which allows the enhanced Mini-ACE to initialise as an online RT with the busy bit set following power turn-on.

Details available from: DDC. Tel: +44 (0) 1635-811140; Fax: +44 (0) 1635-32264; Web site: www.ddc-web.com