New 'ActiveTest' software from JTAG technologies

Soldering & Surface Mount Technology

ISSN: 0954-0911

Article publication date: 1 April 1999

66

Keywords

Citation

(1999), "New 'ActiveTest' software from JTAG technologies", Soldering & Surface Mount Technology, Vol. 11 No. 1. https://doi.org/10.1108/ssmt.1999.21911aad.002

Publisher

:

Emerald Group Publishing Limited

Copyright © 1999, MCB UP Limited


New 'ActiveTest' software from JTAG technologies

New "ActiveTest™" software from JTAG technologies

Keywords JTAG, Software, Testing

JTAG Technologies BV (www.jtag.com) is pleased to announce the launch of a new software tool for a much simplified generation of JTAG/boundary-scan test set-ups.

Traditionally, boundary-scan testing has been the domain of test and production engineers wishing to check the integrity of assembled PCBs by use of the built-in test possibilities offered by JTAG compliant ICs. This has meant that a formal test development program has to be followed involving ATPG tools using cryptic netlist and component data formats.

For the first time JTAG Technologies is attempting to lower the "usage threshold" of boundary-scan test for both designers and test engineers alike, by enabling instant access to the JTAG/boundary-scan features of a board via an interactive Windows® GUI. New ActiveTest™ software requires no knowledge of JTAG TAP-states, BSDL data files, or serial shift sequences etc. By reading an EDIF 200 netlist of your design along with a list of JTAG compliant parts, ActiveTest presents a summary of PCB nets highlighting which nets can be accessed via boundary-scan indicating direction as Input, Output, or I/O. Individual nets can then be grouped using a simple "click and drag" method, and assigned to a label. By using the "add vector" option test patterns can be assigned to the group or groups of nets using either binary, hex, octal or decimal bases. Vectors are then assigned a direction (drive or sense) and can be executed in a single step or continuous loop modes. Logic analyzer-style state or timing diagrams can then be used to display vector updates and vector captures.

This offers an excellent method to "peek and poke" board locations and has proved especially useful during prototype debug of simple interconnects or random logic "clusters", as well as the debug of more involved production tests. Any tests generated using ActiveTest can also be ported to JTAG Technologies' conventional Vector Interface package software or for execution in a production test environment such as LabWindows®, HP VEE etc.

ActiveTest versions are now available for execution on most JTAG Technologies hardware platforms including the popular PM 3705 Explorer and the high-performance PC Plug-in card JT 3710 DataBlaster.

For more information contact: Harry Bleeker, Marketing Director, JTAG Technologies BV, Boschdijk 50, 5612 AN, Eindhoven, The Netherlands. Tel:+ 31 40 295 0870; Fax: + 31 40 246 8471 E-mail:- harry@jtag,nl

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